This invention relates to a reproduction apparatus which drives a disk type recording medium to rotate at a fixed linear velocity to perform data reproduction, and a phase locked loop circuit and a phase locking method applied to a reproduction apparatus of the type mentioned.
A system wherein a disk such as a compact disk (CD) or the like is employed as a recording medium has been popularized. In a system of the type mentioned, recording data for which EFM modulation (Eight to Fourteen Modulation), which is a kind of run length limited codes, has been performed are recorded onto a disk. Further, for an operation of rotating a disk, a CLV (Constant Linear Velocity) system is adopted.
In the related art CLV rotational servo, for example, an EFM signal read out from a disk is inputted to a phase locked loop circuit (hereinafter referred to simply as PLL circuit) to extract a clock, and the extracted clock is compared with a reference clock obtained by a crystal element to obtain rotational error information. Then, the rotational error information is fed back to a spindle motor for rotating a disk so that a rotational condition of a constant linear velocity may be obtained.
In order to allow such a CLV servo circuit as described above to function, the PLL circuit must be locked in a condition wherein a clock is extracted accurately. To this end, a construction for performing rough servo control for pulling, upon starting up of the spindle motor, an EFM signal extracted first into a capture range of the PLL circuit is required. In short, in a disk reproduction apparatus, for example, upon starting of rotation of the spindle, rotational servo control is first performed to some degree by a rough servo circuit, and then at a point of time when the PLL circuit is locked, the CLV servo operation is changed over from the rough servo circuit to an ordinary CLV pulling in servo circuit.
A construction of a CLV servo system for a disk reproduction apparatus is shown in FIG. 1.
Referring to FIG. 1, the CLV servo system includes a rough servo circuit 100 and a CLV velocity detection circuit 110.
In the rough servo circuit 100, an EFM signal reproduced from a disk is first inputted to a pit length measurement circuit 101. The EFM signal is run length limited codes which are defined such that a maximum reversal interval of a code train thereof is 11T and a minimum reversal interval is 3T, and the pit length measurement circuit 101 measures the pit length between edges of the inputted EFM signal with reference to a reference measurement clock produced by a crystal (XTAL) element and supplies information of a measured value to a maximum value holding circuit 102. The maximum value holding circuit 102 selectively holds a maximum value from the measurement information of the pit length inputted from the pit length measurement circuit 101 and outputs the maximum values to a minimum value holding circuit 103 in the following stage. The minimum value holding circuit 103 selectively holds a minimum value from the maximum values inputted thereto from the maximum value holding circuit 102 and outputs the minimum value. Thus held value of the minimum value holding circuit 103 exhibits a minimum pit length from maximum pit lengths obtained by the maximum value holding circuit 102. In other words, even if the EFM signal exhibits reversal intervals longer than 11T due to a read error arising from, for example, a damage to a disk or the like, they are cancelled, and information of a maximum pit length almost close to 11T is obtained.
While information of a pit length close to 11T which is the longest reversal interval is obtained within a certain range by the minimum value holding circuit 103 in this manner, an 11T detection circuit 104 compares the pit length (reversal interval value) held by the minimum value holding circuit 103 with the pit length of 11T which serves as a reference to output an error signal of three values. In short, the 11T detection circuit 104 outputs comparison signals of three different values among three cases including a case wherein the held value by the minimum value holding circuit 103 and the pit length of 11T which serves as a reference are equal to each other, another case wherein the pit length of 11T which serves as a reference is larger and a further case wherein the pit length of 11T which serves as a reference is smaller. An error signal obtained in this manner is supplied as a pull-in servo signal CLV-1 to a spindle motor not shown in FIG. 1 so that rough servo control for a CLV is performed.
The CLV velocity detection circuit 110 includes a sync pattern detection circuit 111, to which, as seen in FIG. 1, an EFM signal and a signal PLCK (of, for example, 4.3218 MHz) which corresponds to a clock outputted from a PLL circuit (not shown in FIG. 1) for clock extraction are inputted.
At the top of one frame (588 bits) of the EFM signal, a sync pattern of 24 bits is encoded. The sync pattern is formed from fixed patterns of 11T, 11T and 2T from the top of the frame. In the sync pattern detection circuit 111, the sync pattern is detected by counting the inputted EFM signal in units of a pit (in other words, counting is performed for each 588 bits) using the signal PLCK as a reference clock.
A detection output of the sync pattern detection circuit 111 is supplied to an interpolation protection circuit 112. The interpolation protection circuit 112 executes processing of interpolation of the sync pattern, window protection and so forth if the sync pattern is not detected at an original position or the sync pattern is detected at a position at which the sync pattern should not be originally present, for example, due to a dropout of the reproduction signal, an influence of jitters or the like.
Information of the sync pattern outputted from the interpolation protection circuit 112 is branched and inputted to a frame sync production circuit 113 and a velocity counter 114. The frame sync production circuit 113 produces a frame sync signal based on the inputted detection signal of the frame sync, and the frame sync signal is utilized for required signal processing and so forth.
Meanwhile, in the velocity counter 114, the frame sync at a timing synchronized with the signal PLCK is counted with a predetermined frequency generated by a crystal element so that velocity error information may be obtained. The velocity error information is outputted as a velocity detection signal CLV-2. The velocity detection signal CLV-2 is supplied to a driver for the spindle motor not shown in FIG. 1 so that CLV control in a condition wherein the sync pattern is detected (that is, in a condition wherein the PLL circuit is locked) can be performed. It is to be noted that, though not shown here, for CLV control, for example, also a phase error signal obtained by comparing the clock produced by the PLL circuit with the predetermined frequency signal of the crystal element in phase is used together with the velocity detection signal CLV-2.
In the CLV servo system having such a construction as described above, for example, upon starting of rotation of the spindle motor, the system of the rough servo circuit 100 is utilized to perform rough servo control to control the speed of rotation of the spindle motor until the PLL circuit is pulled into its capture range as described hereinabove. Then, in a condition wherein the PLL circuit is locked, changing over from the rough servo circuit system to the system of the CLV velocity detection circuit 110 is performed so as to control the velocity of rotation of the disk to a constant linear velocity.
Also another PLL circuit having a wide capture function which contemplates expansion of a capture range and a lock range is known as a PLL circuit for reproducing a bit clock synchronized with an EFM signal. An example of a construction of a PLL circuit having such a wide capture function as mentioned above is shown in FIG. 14. It is to be noted that the PLL circuit shown in FIG. 14 has a construction which allows changing over between a normal mode by ordinary operation in which the capture range is not expanded and a wide mode in which a wide capture function is provided.
Referring to FIG. 14, the PLL circuit 200 shown includes two PLL circuit systems including a system clock PLL circuit 300 and an RF PLL circuit 400.
The system clock PLL circuit 300 includes a divider 302 which divides a reference signal of a predetermined frequency generated by an external quartz oscillator 301 and inputs the divided reference signal as a comparison reference signal to a phase frequency comparator 303. The phase frequency comparator 303 performs comparison in phase and frequency between an oscillation frequency signal of a voltage controlled oscillation circuit (VCO: Voltage Controlled Oscillator) 306 divided by a divider 307.fwdarw.divider 308.fwdarw.variable divider 309 and the reference signal mentioned above and outputs an error signal between them. The error signal is supplied to a terminal T.multidot.N of a switch 304.
The switch 304 is controlled with a normal/wide mode change-over signal outputted, for example, from a system controller not shown so that a terminal Tout thereof is connected alternatively to a terminal T.multidot.W (in a wide mode) or the terminal T.multidot.N (in a normal mode) thereof. To the terminal T.multidot.N, the error signal outputted from the phase frequency comparator 303 is supplied, and to the terminal T.multidot.W, spindle rotation information is supplied. The spindle rotation information is a signal having an information value corresponding to the speed of rotation of a spindle motor not shown for driving a disk to rotate. The signal outputted from the switch 304 is filtered by a low-pass filter 305 and inputted as an error control signal to the VCO 306.
The oscillation frequency of the VCO 306 is controlled with a voltage value as the error control signal. The oscillation frequency is outputted to the divider 307.
A switch 310 is constructed such that a terminal Tout thereof is alternatively connected to a terminal T.multidot.W or another terminal T.multidot.N thereof with a normal/wide mode change-over signal supplied thereto from a system controller not shown similarly to the switch 304. To the terminal T.multidot.W of the switch 310, a frequency signal obtained by dividing the oscillation output of the VCO 306 by means of the divider 307 is supplied, and to the terminal T.multidot.N, the reference signal from the quartz oscillator 301 is supplied. An output from the terminal Tout of the switch 310 is inputted to a divider 401 of the RFPLL circuit 400 which is described below.
In the RFPLL circuit 400, the output of the switch 310 after it passes through the divider 401 and a frequency signal obtained by passing an oscillation frequency signal of a VCO 404 through a divider 405.fwdarw.divider 406 are inputted to a phase comparator 402 and supplied as an error control signal through a low-pass filter 403 to the VCO 404.
To a digital PLL circuit 407, a frequency signal obtained by dividing the oscillation frequency signal of the VCO 404 by means of the divider 405 and an EFM signal reproduced from a disk not shown are inputted, and the digital PLL circuit 407 extracts a clock synchronized with the EFM signal based on a detection signal obtained by performing phase comparison based on the two signals.
As operation of the PLL circuit 200 of the construction described above, operation in the normal mode is such as follows.
In the normal mode, in both of the switch 304 and the switch 310, the terminal Tout is connected to the terminal T.multidot.N.
In this instance, the output of the VCO 306 of the system clock PLL circuit 300 is not supplied to the RFPLL circuit 400 in the following stage. Accordingly, in the normal mode, the system clock PLL circuit 300 is not used as a valid circuit.
In this instance, in the RFPLL circuit 400, the reference signal of the quartz oscillator 301 is inputted as a comparison reference signal to the phase comparator 402 through the switch 310.fwdarw.divider 401. The phase comparator 402 performs phase comparison between the comparison reference signal based on the reference signal of the quartz oscillator 301 and the frequency signal originating from the oscillation frequency signal of the VCO 404 and inputted thereto through the divider 405.fwdarw.divider 406. Consequently, the RFPLL circuit 400 is converged so that an oscillation frequency synchronized with the reference signal of the quartz oscillator 301 may be obtained. The digital PLL circuit 407 utilizes, for example, the oscillation frequency of the VCO 404 to reproduce a clock synchronized with the EFM signal. In particular, the RFPLL circuit 400 side operates, in the normal mode, so that the PLL circuit loop may be converged using the reference signal obtained from the quartz oscillator 301 as a reference.
On the other hand, operation of the PLL circuit 200 in the wide mode is such as follows. In this instance, in both of the switch 304 and the switch 310, the terminal Tout is connected to the terminal T.multidot.W.
Consequently, in the system clock PLL circuit 300, the output of the phase frequency comparator 303 is invalidated, and instead, the spindle rotation information is inputted as an error control signal from the switch 304 to the VCO 306 through the low-pass filter 305. In this instance, the oscillation frequency of the VCO 306 is variably controlled in response to the speed of rotation of the spindle motor.
In the RFPLL circuit 400, in place of the reference signal of the quartz oscillator 301, the frequency signal obtained by dividing the frequency of the VCO 306 by means of the divider 307 is further divided by the switch 310.fwdarw.divider 401 and inputted as a comparison reference signal to the phase comparator 402.
Consequently, the oscillation frequency of the VCO 404 of the RFPLL circuit 400 is controlled so that it may be synchronized with the frequency signal which is based on the VCO 306 on the system clock PLL circuit 300 side. This is an operation of varying the oscillation frequency of the VCO 404 so that it may follow the speed of rotation of the spindle motor. Then, since the digital PLL circuit 407 operates based on the output of the VCO 404, for example, even if the speed of rotation of the disk does not reach a prescribed CLV velocity, an operation of locking the digital PLL circuit 407 so as to be synchronized with a clock of the frequency obtained in accordance with the speed of rotation of the disk is obtained. In other words, the capture range of the PLL circuit is widened. Consequently, for example, even if a condition synchronized with the quartz oscillator 301 is not obtained, as far as the PLL circuit is locked following the speed of rotation of the disk, reading out of data by a signal processing system is possible.
In the CLV servo system having such a construction as described hereinabove with reference to FIG. 1, for example, upon starting of the spindle motor described above, if the CLV servo is lost by a disturbance such as vibrations applied from the outside or the like or if a signal drops for a long period of time, changing over to the system of the rough servo circuit 100 is performed so that rough servo control is started again. However, since the pull-in servo signal CLV-1 of the rough servo circuit 100 can assume only three values as described hereinabove, the rough servo circuit 100 can perform servo control only in a narrow bandwidth of, for example, 1 Hz or less. Consequently, a comparatively long time is required to restore the condition wherein the PLL circuit is locked.
Further, in the CLV servo system having such a construction as described hereinabove with reference to FIG. 1, since two CLV servo circuit systems including the system which includes the CLV velocity detection circuit 110 for ordinary servo control and the system of the rough servo circuit 100 for rough servo control are required naturally, the circuit scale becomes large as much.
Furthermore, in the CLV servo system described hereinabove with reference to FIG. 1, since the rough servo circuit 100 and the CLV velocity detection circuit 110 have considerably different servo characteristics from each other, even if a PLL circuit having a wide capture function which has such a circuit construction as described hereinabove with reference to FIG. 14 is used, and if a disturbance or the like continues, for example, during pull-in servo, the possibility is high that the disk rotation speed error may exceed the follow-up range of the PLL circuit, which puts the PLL circuit out of a lock condition.
Particularly with a portable CD player or the like, the possibility is high that it may suffer from a disturbance caused by rolling along the direction of rotation of the disk, and since the relative variation of the speed of rotation of the disk relative to an optical pickup is rendered significantly by the disturbance, in the lock range obtained by the PLL circuit system shown in FIG. 14 and in the control operation of the CLV servo system shown in FIG. 1, it is insufficient to achieve maintenance of a locked condition or a rapid pull-in operation of CLV servo.
Further, also with the circuit construction of the PLL circuit 200 shown in FIG. 14, since two stages of PLL circuit systems including the system clock PLL circuit 300 and the RFPLL circuit 400 are required, an increase in scale of circuit cannot be avoided similarly to the CLV servo system shown in FIG. 1, and this gives a rise also in cost.